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ST
Sitronix
FEATURES
Direct display of RAM data through the display data RAM. RAM capacity : 33 x 96 = 3168 bits Display duty selectable by select pin 1/33 duty : 33 common x 96 segment 1/17 duty : 17 common x 96 segment High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of 2X/3X/4X , where the step-up voltage reference power supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient -0.15%/C ) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. CR oscillator circuit equipped internally (external clock can also be input) Extremely low power consumption Operating power when the built-in power supply is used (an example) 70uA (VDD - VSS = VDD - VSS2 =3.0 V, Quad voltage, V5 - VDD = - 11.0 V). Conditions: When displays pattern OFF and the normal mode is selected. Power supply operate on the low 1.8 voltage Logic power supply VDD - VSS = 1.8V to 3.3V (+10% Range) Boost reference voltage: VDD - VSS2 = 1.8V to 3.3V Booster maximum voltage limited VOUT= -13V (+10% Range) Liquid crystal drive power supply: VDD - V5 = 4.0V to 13.0 V Wide range of operating temperatures: -40 to 85C CMOS process These chips not designed for resistance to light or resistance to radiation.
ST7533
33 x 96 Dot Matrix LCD Controller/Driver
GENERAL DESCRIPTION
The ST7533 is a single-chip dot matrix LCD drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7533 contain 33x96 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7533 chips contain 33 common output circuits and 96 segment output circuits, so that a single chip can drive a 33x96 dot display (capable of displaying 8 columnsx4 rows of PART NO. ST7533 a 16x16 dot kanji font). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7533 can be used to create the lowest power display system with the fewest components for high-performance portable devices. VRS range -2.1V 0.03V
VRS temperature gradient -0.15%/C
Ver 1.0
1/60
2003/07/21
ST7533
ST7533 Pad Arrangement
Chip Size: 7240m x 1,000 m Origin: Chip Center Bump Pitch: 69.1m(Min.) Bump Size: PAD No. 001005 PAD No. 006064 PAD No. 065070 PAD No. 071083 PAD No. 084088 PAD No. 089100 PAD No. 101196 PAD No. 197208 Bump Height: 18m(Typ) Chip Thickness: 660m 49.1m x 70.5m 56m x 60m 51m x 60m 56m x 60m 49.1m x 70.5m 70.5m x 49.1m 49.1m x 70.5m 70.5m x 49.1m
30um 40um
15 um 15 um 15 um 15 15 um um 15 um
15 15 um um
30um 30um
25um 30um 25um
30um 30um
(-3405, 435) 088 ** * 089 084 083 *** 071 070 065 064 ***** Y 006 005 001 ***
(3385,435)
***
ST7533 PAD DIAGRAM
* * * (-3312,-175)
208
(3266, 162) X (0,0) * * *
100 101
*** 196
197
Ver 1.0
2/60
2003/07/21
ST7533
Pad Center Coordinates (1/33 Duty)
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN Name COM[28] COM[29] COM[30] COM[31] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ VSS VSS VRS VDD VDD V1 X 3290 3221 3152 3083 3014 2919 2843 2767 2691 2614 2538 2462 2386 2310 2234 2157 2081 2005 1929 1853 1777 1701 1624 1548 1472 1396 1320 1244 1168 1091 1015 939 863 787 711 634 558 482 406 330 254 178 101 25 -51 -127 -203 -279 -355 -432 -508 -584 Y 409 409 409 409 409 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 PAD No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PIN Name V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS IRS VDD SEL1 VSS COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] X -660 -736 -812 -889 -965 -1041 -1117 -1193 -1269 -1345 -1422 -1498 -1571 -1642 -1713 -1784 -1855 -1926 -2000 -2076 -2152 -2228 -2305 -2381 -2457 -2533 -2609 -2685 -2762 -2838 -2914 -3011 -3080 -3150 -3219 -3288 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3280 -3211 -3142 -3073 Y 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 409 409 409 409 409 351 282 213 144 75 6 -64 -133 -202 -271 -340 -409 -409 -409 -409 -409
Ver 1.0
3/60
2003/07/21
ST7533
PAD No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 PIN Name SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] X -3004 -2935 -2866 -2797 -2728 -2658 -2589 -2520 -2451 -2382 -2313 -2244 -2175 -2106 -2037 -1967 -1898 -1829 -1760 -1691 -1622 -1553 -1484 -1415 -1346 -1276 -1207 -1138 -1069 -1000 -931 -862 -793 -724 -655 -585 -516 -447 -378 -309 -240 -171 -102 -33 36 106 175 244 313 382 451 520 Y -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 PAD No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PIN Name SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] X 589 658 727 797 866 935 1004 1073 1142 1211 1280 1349 1418 1488 1557 1626 1695 1764 1833 1902 1971 2040 2109 2179 2248 2317 2386 2455 2524 2593 2662 2731 2800 2870 2939 3008 3077 3146 3215 3284 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 Y -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -340 -271 -202 -133 -64 6 75 144 213 282 351
Ver 1.0
4/60
2003/07/21
ST7533
Pad Center Coordinates (1/17 Duty)
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN Name COM[12] COM[13] COM[14] COM[15] COMS1 FRS FR CL /DOF VSS /CS1 CS2 VDD /RES A0 VSS /WR(R/W) /RD(E) VDD D0 D1 D2 D3 D4 D5 D6 D7 VDD VDD VDD VSS VSS VSS2 VSS2 VOUT VOUT CAP3CAP3CAP1+ CAP1+ CAP1CAP1CAP2CAP2CAP2+ CAP2+ VSS VSS VRS VDD VDD V1 X 3290 3221 3152 3083 3014 2919 2843 2767 2691 2614 2538 2462 2386 2310 2234 2157 2081 2005 1929 1853 1777 1701 1624 1548 1472 1396 1320 1244 1168 1091 1015 939 863 787 711 634 558 482 406 330 254 178 101 25 -51 -127 -203 -279 -355 -432 -508 -584 Y 409 409 409 409 409 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 PAD No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PIN Name V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VDD VDD TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 VDD M/S CLS VSS C86 P/S VDD /HPM VSS IRS VDD SEL1 VSS Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] SEG[3] X -660 -736 -812 -889 -965 -1041 -1117 -1193 -1269 -1345 -1422 -1498 -1571 -1642 -1713 -1784 -1855 -1926 -2000 -2076 -2152 -2228 -2305 -2381 -2457 -2533 -2609 -2685 -2762 -2838 -2914 -3011 -3080 -3150 -3219 -3288 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3529 -3280 -3211 -3142 -3073 Y 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 414 409 409 409 409 409 351 282 213 144 75 6 -64 -133 -202 -271 -340 -409 -409 -409 -409 -409
Ver 1.0
5/60
2003/07/21
ST7533
PAD No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 PIN Name SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] X -3004 -2935 -2866 -2797 -2728 -2658 -2589 -2520 -2451 -2382 -2313 -2244 -2175 -2106 -2037 -1967 -1898 -1829 -1760 -1691 -1622 -1553 -1484 -1415 -1346 -1276 -1207 -1138 -1069 -1000 -931 -862 -793 -724 -655 -585 -516 -447 -378 -309 -240 -171 -102 -33 36 106 175 244 313 382 451 520 Y -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 PAD No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 PIN Name SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve COM[8] COM[9] COM[10] COM[11] X 589 658 727 797 866 935 1004 1073 1142 1211 1280 1349 1418 1488 1557 1626 1695 1764 1833 1902 1971 2040 2109 2179 2248 2317 2386 2455 2524 2593 2662 2731 2800 2870 2939 3008 3077 3146 3215 3284 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 3529 Y -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -409 -340 -271 -202 -133 -64 6 75 144 213 282 351
Ver 1.0
6/60
2003/07/21
ST7533
BLOCK DIAGRAM
COM31 SEG95 COMS COM0 SEG0
VDD V1 V2 V3 V4 V5
96 SEGMENT DRIVERS
COMS
33 COMMON DRIVERS
COM output control circuit
HPM
Voltage follower circuit
Display data latch circuit
Page address circuit Line address circuit
Display timing generator circuit
FRS M/S CL DOF FR
V5 VR VRS IRS VOUT CAP1+ CAP1CAP2+ CAP2CAP3+ VSS2
I/O buffer
Voltage Regulator circuit
DISPLAY DATA RAM 33 X 96 = 3186 Bits
Column address circuit
Voltage booster circuit
Power Supply Circuit
Oscillator circuit
CLS
Status VSS
Command decoder
Bus holder
MPU INTERFACE ( Parallel and Serial )
SEL1
E(RD)
RW(WR)
A0
CS1
CS2
/RES
C86
P/S
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
Ver 1.0
7/60
2003/07/21
ST7533
PIN DESCRIPTIONS
Power Supply Pins
Pin Name
VDD VSS VSS2 VRS
I/O
Power Supply Power Supply Power Supply Power Supply
Function
Shared with the MPU power supply terminal Vcc. This is a 0V terminal connected to the system GND. This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. This is the internal-output VREG power supply for the LCD power supply voltage regulator. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) V1 V2 V3 V4 V5
No. of Pins
12 9 2 1
V1, V2, V3, V4, V5
Power Supply
When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. V1 V2 V3 V4 1/33 DUTY 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5 1/17 DUTY 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5
10
LCD Power Supply Pins
Pin Name
CAP1+ CAP1- CAP2+ CAP2- CAP3- VOUT
I/O
O O O O O O
Function
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. IRS = "L" : the V5 voltage regulator internal resistors are not used . IRS = "H" : the V5 voltage regulator internal resistors are used .
No. of Pins
2 2 2 2 2 2
VR
I
2
Ver 1.0
8/60
2003/07/21
ST7533
System Bus Connection Pins
Pin Name D5 to D0 D6 (SCL) D7 (SI)
I/O
Function
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = "L") : D7 : serial data input (SI) ; D6 : the serial clock input (SCL). D0 to D5 are set to high impedance. When the chip select is not active, D0 to D7 are set to high impedance. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = "H": Indicates that D0 to D7 are display data. A0 = "L": Indicates that D0 to D7 are control data. When /RES is set to "L," the settings are initialized. The reset operation is performed by the /RES signal level.
No. of Pins
I/O
8
A0
I
1
/RES
I
1
/CS1 CS2
I
This is the chip select signal. When /CS1 = "L" and CS2 = "H," then the chip select becomes active, and data/command I/O is enabled. * When connected to an 8080 MPU, this is active LOW. (E) This pin is connected to the /RD signal of the 8080 MPU, and the ST7533 series data bus is in an output status when this signal is "L". * When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. * When connected to an 8080 MPU, this is active LOW. (R/W) This terminal connects to the 8080 MPU/WR signal. The signals on the data bus are latched at the rising edge of the /WR signal. * When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = "H": Read. When R/W = "L": Write. This is the MPU interface switch terminal. C86 = "H": 6800 Series MPU interface. C86 = "L": 8080 MPU interface. This is the parallel data input/serial data input switch terminal. P/S = "H": Parallel data input. P/S = "L": Serial data input. The following applies depending on the P/S status: P/S Data/Command A0 A0 Data D0 to D7 SI (D7) Read/Write Serial Clock /RD, /WR Write only X SCL (D6)
2
/RD (E)
I
1
/WR (R/W)
I
1
C86
I
1
P/S
I
"H" "L"
1
When P/S = "L", D0 to D5 fixed to either "H". /RD (E) and /WR (R/W) are fixed to either "H" or "L". With serial data input, It is impossible read data from RAM .
Ver 1.0
9/60
2003/07/21
ST7533
Pin Name I/O Function
Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = "H" : used Internal oscillator circuit . CLS = "L" : used external clock input .(internal oscillator is disable) When CLS = "L", input the display clock through the CL terminal.
This terminal selects the master/slave operation for the ST7533 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation input the timing signals required for the liquid crystal display, Synchronizing the liquid crystal display system. M/S = "H" Master operation M/S = "L" Slave operation
No. of Pins
CLS
I
1
M/S
I
M/S CLS "H" "L" "H" "L" "H" "L"
Oscillator Circuit
Power Supply Circuit
CL
FR
FRS
DOF
1
Enabled Disabled Disabled Disabled
Enabled Output Enabled Input Disabled Input Disabled Input
Output Output Input Input
Output Output Output Output
Output Output Input Input
This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S CLS "H" "L" "H" "L" CL Output Input Input Input 1
CL
I/O
"H" "L"
FR /DOF FRS
O O O
This is the liquid crystal alternating current signal terminal. This is the LCD blanking control terminal. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON and is used in conjunction with the FR terminal. This terminal selects the resistors for the V5 voltage level adjustment. IRS = "H": Use the internal resistors IRS = "L": Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal This is the power control terminal for the power supply circuit for liquid crystal drive. /HPM = "H": Normal mode /HPM = "L": High power mode These pins are DUTY selection.
1 1 1
IRS
I
1
/HPM
I
1
SEL 1 SEL1 I 0 1
DUTY 1/33 1/17
BIAS 1/5 or 1/6 1/5 or 1/6 1
TEST0 ~ 5
I
These are terminals for IC testing . TEST0 (PAD No.65) must connect to VDD TEST1 ~ 5 must floating
6
Ver 1.0
10/60
2003/07/21
ST7533
LCD Driver Pins
Pin Name
I/O
Function
These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5. RAM DATA FR H L H L ---Output Voltage Normal Display VDD V5 V2 V3 VDD Reverse Display V2 V3 VDD V5
No. of Pins
SEG0 to SEG95
O
H H L L Power save
96
These are the LCD common drive outputs. Part No. 33 DUTY 17 DUTY COM COM0 ~ COM31 COM0 ~ COM15 TOTAL 32 16
COM0 to COMn
Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V4, and V5. O Scan Data H H L L Power save FR H L H L ---Output Voltage V5 VDD V1 V4 VDD
COMS
O
These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used.
2
Ver 1.0
11/60
2003/07/21
ST7533
DESCRIPTION OF FUNCTIONS
The MPU Interface Selecting the Interface Type With the ST7533 chips, data transfers are done through an 8-bit parallel data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the "H" or "L" it is possible to select either parallel data input or serial data input as shown in Table 1.
Table 1 P/S H: Parallel Input /CS1 /CS1 CS2 CS2 A0 A0 /RD /RD -- /WR /WR -- C86 C86 -- D7 D7 SI D6 D6 SCL D5~D0 D5~D0 (HZ)
L: Serial Input /CS1 CS2 A0 "--" indicates fixed to either "H" or to "L" The Parallel Interface When the parallel interface has been selected (P/S ="H"), then it is possible to connect directly to either an
8080-system MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either "H" or to "L". Table 2
C86
(P/S=H)
/CS1 /CS1 /CS1
CS2 CS2 CS2
A0 A0 A0
/RD E /RD
/WR R/W /WR
D7~D0 D7~D0 D7~D0
H: 6800 Series L: 8080 Series
Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3. Table 3 Shared A0 1 1 0 0 6800 Series R/W 1 0 1 0 8080 Series /RD 0 1 0 1 /WR 1 0 1 0 Function Reads the display data Writes the display data Status read Write control data (command)
Ver 1.0
12/60
2003/07/21
ST7533
The Serial Interface When the serial interface has been selected (P/S = "L") then when the chip is in active state (/CS1 = "L" and CS2 = "H") the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing.
CS1
The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = "H", the data is display data, and when A0 = "L" then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart.
CS2
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SCL 1 A0 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The ST7533 have two chip select terminals: /CS1 and CS2. The MPU interface or the serial interface is enabled only when /CS1 = "L" and CS2 = "H". When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset.
The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7533. Wait time may not be considered. And, in the ST7533, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2.
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The Busy Flag When the busy flag is "1" it indicates that the ST7533 is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time
(tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible.
Writing MPU WR DATA Internal Timing N N+1 N+2 N+3
BUS Holder Write Signal
N
N+1
N+2
N+3
Reading WR MPU RD DATA N N n n+1
Address Preset
Internal Timing
Read Signal
Column Address
Preset N N
Increment N+1 n n+1
N+2 n+2
Bus Holder
Address Set #n
Dummy Read
Figure 2
Data Read #n
Data Read #n+1
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Display Data RAM The display data RAM stores the dot data for the LCD. It has a 33 (4 page x 8 bit +1) x 96 bit structure. as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the LCD display common direction, there are few constraints at the time of display data transfer when multiple ST7533 are used, thus and display structures can be created easily and with a high degree of freedom.
D0 0 1 1 1 0
Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).
COM0
D1
1
0
0
0
0
COM1
D2
0
0
0
0
0
COM2
D3
0
1
1
1
0
COM3
D4
1
0
0
0
0
COM4
-
-
Display data RAM
Liquid crystal display
Figure 3 The Page Address Circuit Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. The Column Addresses The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementing of column addresses stops with 5FH. Because the column address is independent of the page address, when moving, for example, from page 0 column 5FH to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. As is shown in Figure 4, Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special RAM for icons, and only display data D0 is used. (see Figure 4)
Table 4 SEG Output ADC (D0) "0" (D0) "1" The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM31 output for ST7533 , the detail is shown page.11 The display area is a 33 line area for the ST7533. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. SEG0 SEG 95 0 (H) Column Address 5F(H) 5F(H) Column Address 0 (H)
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Page Address D3 D2 D1 D0 Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00 01 02 03 04 05 06 07 08 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
When the common output is normal
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COMS
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4 ADC Column addres s 03 5C 02 5D D0 D0 5A 5B 5E 5F 57 58 59 0
5D
5D
5E
5B
5A
5F
59
58
57
08
07
06
05
04
01
00
Figure 4
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LCD Out
S87
S88
S89
S90
S91
S92
S93
S94
S95
S0
S1
S2
S3
S4
S5
S6
S7
S8
1
Regardless of the display start line address, 1/33duty => 32th line, 1/17duty =>16th line.
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The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S= "H" and CLS = "H". Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is Two-frame alternating current drive waveform
32 CL 33 1 2 3 4 5 6 28 29 30 31 32 33 1 2 3 4 5 6
status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself.
When CLS = "L" the oscillation stops, and the external clock is input through the CL terminal.
accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit.
FR
VDD V1 COM0 V4 V5 VDD V1 COM1 V4 V5
RAM Data VDD V2 SEGn V3 V5
Figure 5
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The Common Output Status Select Circuit In the ST7533 chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized.
Table 6 Status Normal Reverse Duty 1/33 1/17 COM Scan Direction 1/33 DUTY 1/17 DUTY COM0 COM31 COM0 COM15 COM31 COM0 COM15 COM0
com[0:15] Common output pins com[16:31] Com dir 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 coms 0 1 0 1 com[0:7] com[31:23] com[0:7] com[15:8] com[8:15] com[23:16] com[16:23] com[15:8] com[23:31] com[7:0] com[8:15] com[7:0] coms coms coms coms
reserve reserve
The LCD Driver Circuits These are a 129-channel, that generate four voltage levels for driving the LCD . The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure-6 shows examples of the SEG and COM output wave form.
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FR
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
SEG0
SEG 0 1 2 3 4
SEG1
COM0 to SET0
COM0 to SET1
VDD VSS VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5
Figure 6
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The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the Table 7 voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations.
bit
D2 D1 D0
function Booster circuit control bit Voltage regulator circuit control bit (V/R circuit) Voltage follower circuit control bit (V/F circuit)
Status "1" "0" ON ON ON OFF OFF OFF
The Control Details of Each Bit of the Power Control Set Command Table 8 Use Settings Only the internal power supply is used Only the voltage regulator circuit and the voltage follower circuit are used Only the V/F circuit is used Only the external power supply is used D2 1 0 0 0 D1 D0 1 1 0 0 1 1 1 0
Voltage Voltage Voltage booster regulator follower
ON OFF OFF OFF ON ON OFF OFF ON ON ON OFF
External voltage input VSS2 VOUT, VSS2 V5, VSS2 V1 to V5
Step-up voltage Used Open Open Open
Reference Combinations * The "step-up system terminals" refer CAP1+, CAP1-, CAP2+, CAP2-, and CAP3-. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the ST7533 chips it is possible to product a 2X,3X or 4X step-up of the VDD - VSS2 voltage levels. 4X step-up: Connect capacitor C1 between CAP1+ and CAP1-, between CAP2+ and CAP2-, between CAP1+ and CAP3-, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between VDD and VSS2. 3X step-up: Connect capacitor C1 between CAP1+ and CAP1-, between CAP2+ and CAP2- and between VSS2 and VOUT, and short and shor between CAP3- and VOUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between VDD and VSS2. 2X step-up: Connect capacitor C1 between CAP1+ and CAP1-, and between VSS2 and VOUT, leave CAP2+ open, and short between CAP2-, CAP3- and VOUT to produce a voltage in the negative direction at the VOUT terminal that Is twice the voltage between VDD and VSS2. The step-up voltage relationships are shown in Figure 7
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VSS2 C1 VOUT CAP3C1 CAP1+ C1 CAP1CAP2C1 CAP2+ C1 CAP2+ OPEN CAP2+ ST7533 C1 VOUT CAP3ST7533 CAP1+ C1 CAP1CAP2VSS2 C1 VOUT CAP3ST7533 CAP1+ C1 CAP1CAP2VSS2
4x step-up voltage circuit VDD=0V VSS2=-3V VOUT=4xVSS2=-12V 4x step-up voltage relationships
3x step-up voltage circuit VDD=0V VSS2=-3V VOUT=3xVSS2=-9V 3x step-up voltage relationships
2x step-up voltage circuit VDD=0V VSS2=-3V VOUT=2xVSS2=-6V 2x step-up voltage relationships
Figure 7 * The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7533 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. (VREG thermal gradients approximate -0.15%/C)
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The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7533 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. (VREG thermal gradients approximate -0.15%/C)
(A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |.
V5 = 1 +
( Rb ) VEV Ra Rb =(1 + ) ( 1 - 162 ) VREG Ra [ VEV = ( 1 - 162 ) VREG ]
VDD VEV(constant voltage supply+electronic volume)
Internal Ra V5
Internal Rb
Figure 8
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VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25C is as shown in Table 9. Table 9
Part no. ST7533
Equipment Type Internal Power Supply
Thermal Gradient -0.15 %/C
VREG -2.1V
is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for depending on the electronic volume register settings. Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. Table 10 D5 0 0 0 1 1 1 D4 0 0 0 1 1 1 D3 0 0 0 : : 1 1 1 1 1 1 0 1 1 1 0 1 D2 0 0 0 D1 0 0 1 D0 0 1 0 63 62 61 : : 2 1 0
V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 Register D2 D1 D0 ST7533 (1) -0.15 %/C
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Figures 9, 10 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model.
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V5 UNIT:V
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 00H
Ta = 25 C and booster off ,regulator,follower on VSS=-3V 111 110 101 100 011 010 001 000
V5 voltage regulator internal resistor ratio set D2,D1,D0 Electronic volume registered D5 ~ D0
1FH 3FH
Figure 9 : (1) For ST7533 the Thermal Gradient = -0.15%/C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25C and V5 = -7V for an ST7533 on which Temperature gradient = -0.15%/C. Using Figure 9 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 Contents For V5 voltage regulator Electronic Volume Register D5 D4 D3 D2 D1 D0 ------0 1 0 1 Table 13 V5 Variable Range Notch width Min -8.4 (63 levels) Typ -7.0 (central value) 51 Max -5.1 (0 level) Units [V] [mV] 0 0 1 0 1
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(B) When an External Resistance is Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = "L") by adding resistors Ra' and Rb' between VDD and VR, and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra' and Rb'.
V5 = 1 +
( Rb' ) VEV Ra' Rb' =(1 + ) ( 1 - 162 ) VREG Ra' [ VEV = ( 1 - 162 ) VREG ]
VDD VEV(fixed voltage power supply+electronic volume)
External resistor Ra'
V5
External resistor Rb'
Figure 11 Setup example: When selecting Ta = 25C and V5 = -7 V for ST7533 the temperature gradient = -0.15%/C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then = 31 and VREG = -2.1V so, according to equation B-1,
Rb' = 3.12 Ra' Ra' = 340k Rb' = 1060k
At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.
( Rb' ) ( 1 - 162 ) Ra' 31 Rb' -7V = ( 1 + ) ( 1 - 162 ) Ra' V5 = 1 +
VREG (-2.1)
Moreover, when the value of the current running through Ra' and Rb' is set to 5 uA, Consequently, by equations B-2 and B-3,
Table 14 V5 Variable Range Notch width Min -8.6 (63 levels) Typ -7.0 (central value) 52 Max -5.3 (0 level) Units [V] [mV]
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(C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra' and Rb', to set the liquid crystal drive voltage V5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments ( R2).
V5 = 1 +
( R3+R2-R2 ) VEV R1+R2 R3+R2-R2 =(1 + 1R1+R2 ) ( 162 ) [ VEV = ( 1 - 162 ) VREG ]
VREG
VDD VEV(fixed voltage power supply+electronic volume)
Ra'
External resistor R1 External resistor R2 R2 VR
V5
Rb'
External resistor R3
Figure 12 Setup example: When selecting Ta = 25C and V5 = -5 to -9 V (using R2) for an ST7533 the temperature gradient = -0.15%/C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then = 31 and VREG = -2.1 V so, according to equation C-1, when R2 = 0 , in order to make V5 = -9 V,
With this, according to equation C-2, C-3 and C-4,
R1 = 264k R2 = 211k R3 = 925k
The V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15.
R3+R2 -9V= 1 + R1
(
)(
31 1162
)
(-2.1)
When R2 = R2, in order to make V = -5 V,
-5V = 1 +
(
R3 R1+R2
31 ) ( 1 - 162 )
Min -8.7 (63 levels)
(-2.1)
Table 15
When the current flowing VDD and V5 is set to 5 uA, V5 Variable Range Notch width Typ -7.0 (central value) 53 Max -5.3 (0 level) Units [V] [mV]
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* When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. * The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = "L"). When the V5 voltage regulator internal resistors are used (i.e. when the IRS terminal = "H"), then the VR terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. The LCD Voltage Generator Circuit The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, High Power Mode The power supply circuit equipped in the ST7533 chips has very low power consumption (normal mode: HPM = "H"). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to "L" (high power mode) can improve the quality of the display. We recommend that The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure 13 is recommended for shutting down the internal power supply, first placing the
Sequence Step1 Step2 End
when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally.
power supply in power saver mode and then turning the power supply OFF.
Command address D7 D6 D5 D4 D3 D2 D1 D0 1 01 01 11 0 1 01 00 10 1
Details (Command, status) Display OFF Display all points ON Internal power supply OFF
Power saver commands (compound)
Figure 13
The temperature grade of the Internal Power Supply for ST7533 (-0.15%/C) :
9.40V 8.46V 7.60V V5 0V
Ta=-40C , V5=9.40V Ta=25C , V5=8.46V
Ta=85C , V5=7.60V
-40C
-20C
0C
25C
Figure 14
50C
85C
Ta
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Reference Circuit Examples Figure 15 shows reference circuit examples. 1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor (2) When the voltage regulator internal resistor is used. is not used. (Example where VSS2 = VSS, with 4x step-up) (Example where VSS2 = VSS, with 4x step-up)
VDD VDD
IRS
M/S
IRS
M/S
VSS2 VSS C1 VOUT CAP3C1 CAP1+ C1 CAP1CAP2+ C1 CAP2R3 C1 CAP5C1 CAP4C1 VSS C1
VSS2 VOUT CAP3CAP1+ CAP1CAP2+ CAP2CAP4CAP5-
ST7533
ST7533
V5 VR VDD VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5
V5 R2 VDD R1 VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 VR
2. When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor (2) When the V5 voltage regulator internal resistor is not used. is used.
VDD VDD
IRS
M/S
IRS
M/S
VSS2 VSS VOUT External power supply CAP3CAP1+ CAP1CAP2+ CAP2R3 V5 R2 VDD R1 VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 C2 C2 C2 C2 C2 VR CAP4CAP5External power supply VSS
VSS2 VOUT CAP3CAP1+ CAP1CAP2+ CAP2CAP4CAP5-
ST7533
VDD
ST7533
V5 VR
VDD V1 V2 V3 V4 V5
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3. When the V/F circuit alone is used
VDD VSS IRS M/S IRS M/S
4. When the built-in power is not used
VDD
VSS2 VSS VOUT CAP3CAP1+ CAP1CAP2+ External power supply CAP2CAP4CAP5-
VSS2 VOUT CAP3CAP1+ CAP1CAP2+ CAP2CAP4CAP5-
ST7533
ST7533
V5 VR VDD VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5
V5 VR VDD VDD V1 V2 External power supply V3 V4 V5
5. When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V4 which are output from the
VDD,V0
built-in voltage follower. Examples of shared reference settings When V5 can vary between -8 and 12 V
Item
R4 R4
Set value 1.0 to 4.7 0.1 to 4.7
units uF uF
c1 c2
V1 V2 V3 V4
C2
C1 and C2 are determined by the size of the LCD being driven
ST7533
R4
R4
V5
crystal display and the drive waveform. Reference set value R4: 100K ~ 1M It is recommended to set an optimum resistance value R4 taking the liquid Figure 15 * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings: * Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside. * Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value. * Next turn all the power supplies ON and determine C1.
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The Reset Circuit When the /RES input comes to the "L" level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = "L") 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: 1/33 DUTY = 1/6 bias 1/17 DUTY = 1/5 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = "L") 8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb separation 10. Output conditions of SEG and COM terminals SEG=VDD , COM=VDD 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0) 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on ST7533,it is necessary that /RES is "H" when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when /RES is "L," and the external power supply short-circuits to VDD when /RES is "L." While /RES is "L," the oscillator and the display timing generator stop, and the CL, FR, FRS and /DOF terminals are fixed to "H." The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between VDD and V5. When the internal liquid crystal power supply circuit is not used on other models of ST7533 series, it is necessary that /RES is "L" when the external liquid crystal power supply is turned on. While /RES is "L," the oscillator works but the display timing generator stops, and the CL, FR, FRS and /DOF terminals are fixed to "H." The terminals D0 to D7 are not affected.
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COMMANDS
The ST7533 identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the /RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an "H" signal is input to the R/W terminal and placed in a write mode when a "L" signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes "1(H)". In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. Display ON/OFF This command turns the display ON and OFF. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 Setting
1 Display ON 0 Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in "The Line Address Circuit". E A0 0 RD 1 R/W WR 0 D7 0 D6 1 D5 0 D4 0 0 0 1 1 Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 Page address 0 1 2 3 4 D3 0 0 0 1 1 1 1 1 1 0 1 D2 0 0 0 D1 0 0 1 D0 0 1 0 Line address 0 1 2 30 31
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Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 5FH. This does not change the page address continuously. See the function explanation in "The Column Address Circuit," for details. E High bits Low bits A0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 1 A7 A6 0 A3 A2 A5 A4 0 A1 A0 0 0 0 0 Status Read E A0 0 RD 0 R/W WR 1 D7 BUSY D6 ADC D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 11 11 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1
RD WR 1 0
Column address 0 1 2 94 95
ON/OFF RESET
BUSY
BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process. BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for BUSY conditions. This shows the relationship between the column address and the segment driver. 0: Normal (column address n SEG n) 1: Reverse (column address 95-n SEG n) (The ADC command switches the polarity.) ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset command. 0: Operating state 1: Reset in progress
ADC
ON/OFF
RESET
Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by "1" after the write, the MPU can write the display data. E A0 1 RD 1 R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data
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Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by "1" after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in "Display Data RAM" for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E A0 1 RD 0 R/W WR 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data
ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (Figure 4) for the detail. Increment of the column address (by "1") accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 Setting Normal Reverse
Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 Setting RAM Data "H" LCD ON voltage (normal) RAM Data "L" LCD ON voltage (reverse)
Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 Setting Normal display mode Display all points ON
When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the Power Save section.
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LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. E A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 1 Select Status 1/33duty 1/6 bias 1/5 bias 1/17duty 1/6 bias 1/5 bias
Read/Modify/Write This command is used paired with the "END" command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor.
E A0 0 RD 1
R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 0 0
* Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Page address set Column address set
Read-modify-write cycle
Dummy read Data read Data write NO
Changes Finished ? YES END
Figure 24 Command Sequence For read modify write
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Return Column address N N+1 N+2 N+3 N+m N End
Read-modify-write mode set Figure 25 End
This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E A0 0 Reset This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in "Reset" for details. The reset operation is performed after the reset command is entered. E A0 0 RD 1 R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 1 0 RD 1 R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 1 0
The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset command must not be used instead. Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in "Common Output Mode Select Circuit." E R/W A0 RD WR 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 1 * * * Selected Mode
1/33duty
1/17duty
Normal COM0COM31 COM0COM15 Reverse COM31COM0 COM15COM0
* Disabled bit
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Power Controller Set This command sets the power supply circuit functions. See the function explanation in "The Power Supply Circuit," for details E A0 RD R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V5 voltage regulator internal resistor ratio. For details, see the function explanation is "The Voltage Regulator circuit " and table 11 . E A0 RD R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 Rb/Ra Ratio Small Large Selected Mode Booster circuit: OFF Booster circuit: ON Voltage regulator circuit: OFF Voltage regulator circuit: ON Voltage follower circuit: OFF Voltage follower circuit: ON
The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released.
E A0 0 RD 1
R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 1
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Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set.
E A0 RD
R/W WR D7 D6 D5 D4 D3 D2 D1 D0 * * * * * * * * * * 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 1 | V5 | Small
0
1
0
Large * Inactive bit (set "0") When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) The Electronic Volume Register Set Sequence
electronic volume mode set
electronic volume register set Electronic volume mode clear NO Set complete ? YES Figure 26 Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. T h i s m o d e is clea red whe n dat a is se t in the r egist er by th e st atic ind ic at or reg is te r set com mand .
E A0 0 RD 1
R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 0 0 1 Static Indicator OFF ON
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Static Indicator Register Set This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. E A0 0 RD 1 R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 * * * * * * 0 0 1
1
Indicator Display State OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on)
0 1 0
1
* Disabled bit (set "0") Static Indicator Register Set Sequence
Static indicator mode set
Static indicator register set Static indicator mode clear NO Set complete ? YES Figure 27 Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 28 for power save off sequence. Static indicator OFF Display OFF Static indicator ON Display OFF
Display all point ON
Display all point ON
Sleep mode
Standby mode
Power save OFF Display all point OFF Static indicator ON (2 bytes) Sleep mode cancel Figure 28
Power save OFF ( Display all point OFF )
Standby mode cancel
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Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The ST7533 series chips have a liquid crystal display blanking control terminal /DOF. This terminal enters an "L" state when the power saver mode is launched. Using the output of /DOF, it is possible to stop the function of an external power supply circuit.
NOP Non-OPeration Command
E A0 0 Test RD 1
R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 1 1
This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a "L" signal to the /RES input by the reset command or by using an NOP.
E A0 0 RD 1
R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 * *
* Inactive bit Note: The ST7533 maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the ST7533 . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise.
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Table 16: Table of ST7533 Commands Command Code Command A0 RD WR (1) Display ON/OFF (2) Display start line set (3) Page address set (4) Column address set upper bit Column address set lower bit (5) Status read (6) Display data write (7) Display data read (8) ADC select (9) Display normal/ reverse (10) Display all points ON/OFF (11) LCD bias set (12) Read/modify/write (13) End (14) Reset (15) Common output mode select (16) Power control set (17) V5 voltage regulator internal resistor ratio set (18) Electronic volume mode set Electronic volume register set (19) Static indicator ON/OFF Static indicator register set (20) Power saver (21) NOP (22) Test 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 * 0 * 1 * 1 * 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 10101110 1 0 1 0 0 1 0 0 0 Display start address 1 0 0 1 Page address Function LCD display ON/OFF 0: OFF, 1: ON Sets the display RAM display start line address Sets the display RAM page address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. Reads the status data Writes to the display RAM Reads from the display RAM 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 * Sets the display RAM address SEG output correspondence 0: normal, 1: reverse Sets the LCD display normal/ reverse 0: normal, 1: reverse Display all points 0: normal display 1: all points ON Sets the LCD drive voltage bias ratio 0: 1/6 bias, 1: 1/5 bias (ST7533) Column address increment At write: +1 At read: 0 Clear read/modify/write Internal reset Select COM output scan direction 0: normal direction 1: reverse direction Select internal power supply operating mode Select internal resistor ratio(Rb/Ra) mode Set the V5 output voltage electronic volume register (Note) *: disabled data
1 Most significant column address 0 Least significant column address 0 0 0 0
Status
Write data Read data 0 0 0 0 0 0 0 0
1 1 1 1 0 0
1 1 1 1 0 0
1 1 1 0 1 1
0 0 0 0 0 0
0 1 0 0 1 1 0
0 1 0 *
0 1 1 *
Operating mode Resistor ratio
0
1
0
1 0 1
0000001 0 Electronic volume value 0 0 1 0 0 0 1 0 1 0
0
1
0 0
0 0: OFF, 1: ON 1 0 0 Mode Set the flashing mode Display OFF and display all points ON compound command Command for non-operation Command for IC test. Do not use this command
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COMMAND DESCRIPTION
Instruction Setup: Reference
(1) Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1. When the built-in power is being used immediately after turning on the power: Turn ON the power and keeping the /RES pin = "L" When the power is stabilized Release the reset state. (/RES pin = "H") Waiting reset circuit stabilized (<1ms) Initialized state (Default) *1
Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4
Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6
Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms.
Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting
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2. When the built-in power is not being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the /RES pin = "L". When the power is stabilized Release the reset state. (/RES pin = "H") Waiting reset circuit stabilized (<1ms)
Initialized state (Default) *1 Power saver START (multiple commands) *8
Arrange to start the power saver within 5ms after releasing the reset state. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms.
Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4
Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6
Power saver OFF *8 Arrange to start power control setting within 5ms after turning OFF the power saver.
Function setup by command input (User setup) (16) Power control setting *7
This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state. Command description; Power saver START (multiple commands)
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(2) Data Display
End of initialization
Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11
Function setup by command input (User setup) (6) Display data write *12
Function setup by command input (User setup) (1) Display ON/OFF *13
End of data display Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white.
(3) Power OFF *14
Optional status Set the time (tL) from reset active to turning off the VDD VSS power (VDD - VSS = 1.8V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1V) of the LCD panel. For tH, refer to the of this event. When tH is too long, insert a resistor between V5 and VDD to reduce it.
Function setup by command input (User setup) (20) Power save *15
Reset active (RES pin = "L")
VDD - VSS power OFF
Notes: Reference items *14: The logic circuit of this IC's power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures: * After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC's power supply (VDD - VSS). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save
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Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Refresh sequence
Reset command or NOP command
Set all commands to the ready state
Refreshing of DRAM
Precautions on Turning off the power 1) Power Save (The LCD powers (VDD - V5) are off.) Reset input Power (VDD - VSS) OFF * Observe tL > tH. * When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver's discharging capacity.
Reset Power save tL VDD 1.8V Power Off
RES
VDD SEG Since the power (VDD-VSS) is cut off,the output comes not to be fixed. VDD COM
V1 V2 V3 V4 V5
About 1V:below Vth of the LCD Panel
tH
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2) Reset (The LCD powers (VDD - VSS) are off.) Power (VDD - VSS) OFF * Observe tL > tH. * When tL < tH, an irregular display may occur. For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver's discharging capacity.
Reset Power Off tL VDD 1.8V
RES
VDD SEG Since the power (VDD-VSS) is cut off,the output comes not be fixed. VDD COM
V1 V2 V3 V4 V5
About 1V:below Vth of the LCD Panel
tH
V5 voltage falling (discharge) time (tH) after the process of operation power save reset. V5 voltage falling (discharge) time (tH) after the process of operation reset.
100 VDD-VSS(V)
V5 voltage falling time (mSec)
1.8 2.4 50 3.0 4.0 5.0
0
0.5 C2 : V1 to V5 capacity (uF)
1.0
Figure 31
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ABSOLUTE MAXIMUM RATINGS
Unless otherwise noted, VSS = 0V Table 17 Parameter Power Supply Voltage Power supply voltage (VDD standard) Power supply voltage (VDD standard) Power supply voltage (VDD standard) Input voltage Output voltage Operating temperature Storage temperature
VCC
Symbol VDD VSS2 V5, VOUT V1, V2, V3, V4 VIN VO TOPR
Conditions -0.3 ~ +5.0 -4.0 ~ -1.8 -16.0 ~ +0.3 V5 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -40 to +85 -55 to +125
VDD
Unit V V V V V V C C
Bare chip
VDD
TSTR
GND
VSS
VSS2,V1 to V4
V5.,VOUT System (MPU) side ST7533 chip side
Figure 30 Notes and Cautions 1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD V1 V2 V3 V4 V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.
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DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V 10%, Ta = -40 to 85C Table 18 Item Operating Voltage (1) Symbol Vss Condition Min. -3.3 Rating Typ. -- Max. -1.8 Units V Applicable Pin Vss*1
Operating Voltage (2)
VSS2
(Relative to VDD)
-3.3 -13.0
-- -- -- -- -- -- -- -- -- -- 2.0 3.2 0.01 0.01 5.0 24 24
-1.8 -4.0 VDD 0.6 x V5 VDD 0.2 x VDD VDD 0.2 x VDD 1.0 3.0 3.5 5.4 2 10 8.0 27 27
V
VSS2 V5 *2
Operating Voltage (3)
VSS2
(Relative to VDD)
0.4 x V5 V5
V
V1, V2 V3, V4
High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Static Consumption Current Output Leakage Current Input Terminal Capacitance Oscillator Frequency Internal Oscillator External Input
VIHC VILC VOHC IOH = -0.5 Ma VOLC IOL = 0.5 mA ILI ILO RON VIN = VDD or VSS VIN = VDD or VSS Ta = V5 = -13.0 V 25C (Relative V5 = -8.0 V To VDD) V5 = -13.0 V(Relative To VDD) Ta = 25C , f = 1 MHz 1/33 duty , Ta = 25C fCL
0.8 x VDD VSS 0.8 x VDD VSS -1.0 -3.0 -- -- -- -- -- 17 17
V V V V A A K
*3 *3 *4 *4 *5 *6 SEGn COMn *7 VSS, VSS2 V5
ISSQ I5Q CIN fOSC
A A pF kHz kHz
*8 CL
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Table 19 Item Input voltage Supply Step-up output voltage Circuit Voltage regulator Circuit Operating Voltage Voltage Follower Circuit Operating Voltage Base Voltage Internal Power Symbol VSS2 Condition (Relative To VDD) Min. -3.3 -13.0 -13.0 -13.0 -2.07 Rating Typ. -- -- -- -- -2.10 Max. -1.8 -- -6.0 -4.0 -2.13 Units V V V V V Applicable Pin VSS2 VOUT VOUT V5 * 9 *10
VOUT (Relative To VDD) VOUT (Relative To VDD) V5 VRS (Relative To VDD) Ta = 25C , (Relative To VDD) -0.15%/C
* Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Table 20 Rating Test pattern Symbol Condition Units Notes Min. Typ. Max. Display Pattern OFF Display Pattern Checker
IDD IDD
VDD = 3.0 V, V5 - VDD = -11.0 V VDD = 3.0 V, V5 - VDD = -11.0 V
-- --
4 7
12 21
A A
*11 *11
* Dynamic Consumption Current : During Display, with the Internal Power Supply ON Table 21 Rating Test pattern Symbol Condition Min. Typ. Display Pattern OFF Display Pattern Checker
Max. 110
Units Notes
IDD
VDD = 3.0 V, Quad step-up voltage. V5 - VDD = -11.0 V VDD = 3.0 V, Quad step-up voltage. V5 - VDD = -11.0 V
Normal Mode High-Power Mode Normal Mode High-Power Mode
-- -- -- --
70 90 95 130
A 150 130 A 180
*12
IDD
*12
* Consumption Current at Time of Power Saver Mode : VSS = -3.0 V 10% Table 22 Item Sleep mode Standby Mode Symbol Condition Ta = 25C Ta = 25C Min. -- -- Rating Typ. 0.1 5 Max. 4 10 Units A Notes
IDD IDD
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* The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR Table 23 Item fCL fFR
1/33 DUTY
Used internal oscillator circuit Used external display clock Used internal oscillator circuit Used external display clock
fOSC / 8
External input (fCL)
fOSC / (8*33) fCL / 264 fOSC / (16*17) fCL / 272
1/17 DUTY
fOSC / 16
External input (fCL)
(fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S and C86, P/S, /DOF, /RES, IRS, and /HPM terminals. *4 The D0 to D7, FR, FRS, /DOF, and CL terminals. *5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the ST7533 , the temperature range approximately -0.15%/C. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The ST7533 is 1/5 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a ST7533 having the VREG temperature gradient is -0.15%/C when the V5 voltage regulator internal resistor is used.
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TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8 CS1 (CS2="1") tCYC8 tCCLR,tCCLW WR,RD
tAH8
tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 37 Table 24 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD = 3.3V , Ta =25C) Rating Units Min. Max. 0 0 240 80 80 140 80 40 10 CL = 100 pF CL = 100 pF -- 5 -- -- 70 50 -- -- -- -- -- -- ns
tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8
RD
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Table 25 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD = 2.7 V , Ta = 25C ) Rating Units Min. Max. 0 0 400 220 180 220 180 40 15 CL = 100 pF CL = 100 pF Table 26 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD = 1.8V , Ta = 25C ) Rating Units Min. Max. 0 0 640 360 280 360 280 80 30 CL = 100 pF CL = 100 pF -- 10 -- -- 240 200 -- -- -- -- -- -- ns -- 10 -- -- -- -- -- -- -- -- -- 140 100 ns
tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8
RD
tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1 being "L" (CS2 = "H") and WR and RD being at the "L" level.
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A0 R/W tAW6 CS1 (CS2="1") tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tDH6 tAH6
tACC6 D0 to D7 (Read)
tOH6
System Bus Read/Write Characteristics 2 (For the 6800 Series MPU) Figure 38 Table 27 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD = 3.3 V , Ta = 25C ) Rating Units Min. Max. 0 0 240 80 80 80 140 40 10 CL = 100 pF CL = 100 pF -- 5 -- -- 70 50 -- -- -- -- -- -- ns
tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6
RD
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Table 28 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD = 2.7V , Ta =25C ) Rating Units Min. Max. 0 0 400 220 180 220 180 40 15 CL = 100 pF CL = 100 pF Table 29 Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol Condition (VDD =1.8V , Ta =25C ) Rating Units Min. Max. 0 0 640 360 280 360 280 80 30 CL = 100 pF CL = 100 pF -- 10 -- -- -- -- -- -- -- -- -- 240 200 ns -- 10 -- -- -- -- -- -- -- -- -- 140 100 ns
tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6
RD
tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being "L" (CS2 = "H") and E.
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The Serial Interface
tCCSS CS1 (CS2="1") tCSH
tSAS A0 tSCYC tSLW SCL
tSAH
tSHW tf tSDS SI tr tSDH
Figure 39 Table 30 Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CS SCL Signal Symbol Condition (VDD = 3.3V, Ta =25C ) Rating Units Min. Max. 50 -- 25 25 20 10 20 10 20 40 -- -- -- -- -- -- -- -- ns
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
Table 31
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time
Signal
Symbol
Condition
SCL
A0 SI CS
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
(VDD =2.7V , Ta =25C ) Rating Units Min. Max. 100 -- 50 50 30 20 30 20 30 60 -- -- -- -- -- -- -- -- ns
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Table 32 Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CS SCL Signal Symbol Condition (VDD = 1.8V , Ta = 25C ) Rating Units Min. Max. 200 -- 80 80 60 30 60 30 40 100 -- -- -- -- -- -- -- -- ns
TSCYC TSHW TSLW TSAS TSAH TSDS TSDH TCSS tCSH
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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Reset Timing
tRW RES
tR Internal status During reset Reset complete
Figure 41 Table 36 Item Reset time Reset "L" pulse width Signal RES Symbol Condition (VDD = 3.3V , Ta = -40 to 85C ) Rating Units Min. Typ. Max. us -- -- 1.0 us 1.0 -- --
tR tRW
Table 37
Item Reset time Reset "L" pulse width
Signal RES
Symbol
Condition
tR tRW
Table 38
(VDD = 2.7V , Ta = -40 to 85C ) Rating Units Min. Typ. Max. us -- -- 2.0 us 2.0 --
Item Reset time Reset "L" pulse width
Signal RES
Symbol
Condition
tR tRW
(VDD = 1.8V , Ta = -40 to 85C ) Rating Units Min. Typ. Max. us -- -- 3.0 us 3.0 -- --
*1 All timing is specified with 20% and 80% of VDD as the standard.
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THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7533 Series can be connected to either 80X86 Series MPUs or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7533 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7533 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs
VDD VCC A0 A1 to A7 IORQ DO to D7 RD WR RES RESET Decoder A0 CS1 CS2 DO to D7 RD WR RES VSS VSS VDD C86
P/S
GND
Figure 42-1 (2) 6800 Series MPUs
VDD VCC A0 A1 to A15 VMA DO to D7 E R/W RES RESET Decoder A0 CS1 CS2 DO to D7 E R/W RES VSS VSS VDD C86 ST7533 P/S
VDD or VSS VCC A0 A1 to A7 MPU Decoder A0 CS1 CS2 VDD C86 ST7533 P/S VSS VSS
MPU
GND
Figure 42-2 (3) Using the Serial Interface
Port 1 Port 2 RES GND RESET
SI SCL RES
Figure 42-3
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CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE)
The liquid crystal display area can be enlarged with ease through the use of multiple ST7533 Series chips. Use a same equipment type. (1) ST7533 (master) ST7533 (slave)
VDD
M/S CLS
FR
CLS
FR
M/S
ST7533 Master
DOF
DOF
Output
Input
ST7533 Slave
CL
CL
VSS
VDD
M/S CLS
FR
CLS
FR
M/S
ST7533 Master
DOF
DOF
Output
Input
ST7533 Slave
CL
CL
VSS
Figure 43-1
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(2) Single-chip Structure
96 X 33
Dots
ST7533 Master
Figure 43-2 (3) Double-chip Structure
192 x 33 Dots
COM ST7533 Master
SEG
SEG
Figure 43-3
COM ST7533 Slave
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Revisions
Version 0.1 Version 0.2 - Preliminary. - update Pad Center Coordinates page 2,3,4.
Version 0.2a - update PIN DESCRIPTIONS M/S. Version 0.2b - update ABSOLUTE MAXIMUM RATINGS & DC CHARACTERISTICS. Version 0.2c - update Master and Slave reference example. Version 0.3 - update Pad Center Coordinates (1/33 , 1/17 Duty) page 3,4,5,6 and page-18. Version 0.3a - update Pad diagram page2 and v5 regulator voltage diagram page24 Version 0.3b - Logic power supply VDD - VSS = 1.8V to 3.3V (+10% Range) , VOUT= -13V (+10% Range) Version 0.3c - Modify page-27 The temperature grade of the Internal Power Supply for ST7533 (-0.05%/C) Figure 14 Version 0.3d - Delete page-40 Figure 29 Version 0.4 Version 0.5 Version 0.6 Version 1.0 - Modify VRS temperature gradient (-0.15%/C) and Reset "L" pulse width - Delete shipping forms include bare chip and TCP - Modify page-10 The TEST0(PAD No.65) must connect VDD - Modify Tdh (data hold time) and page41,42 initial flow , datasheet version change version 1.0
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